Date of birth project
introduction
A notable project of the electronics course was the “Date of Birth” assignment where students designed a circuit using NAND/NOR/XOR/XNOR gates as well as another iteration with traditional AOI Logic Gates to make a cathode seven segment display list the digits of the students date of birth in sequential order through certain inputs on switches. Each group consisted of two people but both birth dates had to be displayed on seperate simulations and programs.
K-Mapping, Truth Tables, and the seven segment display
As standard for every circuit designed, a truth table listing every possible scenario, given the inputs, was listed. In sequential order, 0 0 0 being the first digit of the date, was charted with the desired segments that create the number to be activated. Since my first digit is 1 for October, B and C had to be activated, thus the table listed B and C as 1 and the rest zero. This process was repeated to form “10-06-00.”
Below is the Karnaugh, or K, Mapping of the individual segments. This graphical representation of each segment would give the simplified boolean equation that would represent the desired outputs for the intended function. Essentially, a much more effective and easily digestible truth table.
DOB Pld
After breadboarding the design, the PLD, “Programmable Logic Device,” was introduced and the logic design was re-coded to follow the functions of a PLD.
Realistically, a PLD is a much more meaningful testing bed for most modern day applications of electronics and technology since it utilizes an IC Chip which offers much more versatility than a series of interconnecting wires and gates.
Unlike Multisim, the PLD offers a much more powerful program with access to input gates with more than two inputs as well as PIO slots which would act as inputs and outputs, drastically simplifying the output complexity of the design.